1. Field of the Invention
The present invention relates to a latch, and more particularly, to a latch capable of being operated in a high frequency.
2. Description of the Related Art
In an integrated circuit, clock signals having different frequencies are often utilized to perform different operations. As is known, the phase locked loop (PLL)/synthesizer is widely used for generating the above-mentioned clock signals having different frequencies.
As known by those skilled in the art, the PLL/synthesizer comprises a frequency divider, which is utilized to divide the frequency generated by the inner VCO (voltage controlled oscillator). Through the above-mentioned mechanism, the PLL can output a clock signal having a wanted frequency.
In general, the frequency divider is often implemented by D-type flip-flops. Please refer to FIG. 1, which is a diagram of a frequency divider 100 having a divisor 2 according to the prior art. As shown in FIG. 1, the frequency divider 100 is implemented by a D-type flip-flop 200. The input end Q′ and the input end D of the D-type flip-flop 200 are coupled to each other. In this way, as shown in FIG. 1, the frequency of the output signal outputted from the output end Q′ is twice of that of the clock signal CK inputted into the clock input end. Since the operation and function of the D-type flip-flop are well known, and thus omitted here.
In addition, the frequency divider is often operated in a high frequency. Therefore, in the actual implementation, the D-type flip-flop is often implemented by a current mode logic (CML) circuit, which comprises two latches. Please note, the related theory and the conventional circuit structure can be referred to the page 290 of RF Microelectronics (ISBN: 0-13-887571-5) written by Behzad Razavi, and further illustration is omitted here.
However, if the function of the above-mentioned frequency divider 100 should be achieved, the input end and the output end of the above-mentioned D-type flip-flop are coupled together such that the feedback loop (it is equivalent to the feedback loop from the output end Q to the input end D shown in FIG. 1) is established. As mentioned previously, the CML D-type flip-flop is more appropriate for the high-frequency operation, but it still has many restrictions.
For example, if the circuit designer wants to design a frequency divider having a devisor 4, the most frequently-used method is to connect two frequency divider having a devisor 2 (that is, to connect two D-type flip-flops).
But, if the frequency divider having the devisor 4 should be operated in a high frequency, a conventional solution is to reduce the inner load (it could be a resistor or passive device) of the D-type flip-flops such that the RC constant is also reduced. However, a larger biasing current is needed such that enough signal amplitude is provided to the following D-type flip-flop.
Please note, the operation of raising the biasing current often encounters following problems:
The first solution is to raise the biasing current without adjusting the W/L ratio of inner transistors. But this reduces the voltage difference VDS of the biasing current source (such as a current mirror), and may further make the biasing current source be in the triode region such that the current cannot be increased more, and the operational frequency cannot be raised, either.
The second solution is to raise the biasing current with adjusting the W/L ratio of inner transistors. However, this makes the parasitic capacitor of the gate of the inner transistors larger. Unfortunately, the increasing parasitic capacitor becomes the load of the previous D-type flip-flop such that the RC delay of the previous D-type flip-flop increases accordingly. This also limits the operational frequency of the entire circuit.